Computer Pipelining
Computer pipelining was first introduced by Intel in the 486 chip. The way a pipeline operates is analogous to an industrial assembly line. Within the CPU, a series of circuit units with distinct functions forms an instruction processing pipeline; an x86 instruction is broken down into five or six steps, which are then executed sequentially by these units. This enables the completion of an instruction within a single CPU clock cycle, thereby increasing the CPU's processing speed. In the classic Pentium processor, each integer pipeline consists of four stages-instruction prefetch, decode, execute, and write-back-while the floating-point pipeline comprises eight stages.
Pipelining is a key technology widely used in microprocessors (CPUs). It describes the method by which instructions are executed within the CPU; to understand pipelining, one must first understand instructions and the process of their execution.
Computer Instructions
A computer instruction is a specific set of binary data that tells the CPU what to do. If the CPU is likened to a manufacturing plant, an instruction is akin to a customer order; it triggers a series of actions within the CPU "factory," ultimately yielding a computational result-the finished product. How does this actually work? First, there must be a department to receive orders-the CPU's instruction fetch unit; second, there must be a workshop to fulfill the orders-the CPU's instruction execution unit. In a factory, the production of an item is broken down into multiple manufacturing steps; similarly, an instruction is converted into a series of corresponding micro-operations within the CPU. Completing these micro-operations in sequence constitutes the execution of the entire instruction.
Instruction Execution
In low-end CPUs, instruction execution is serial; simply put, one instruction is completed before the next begins. This is like the aforementioned factory in its early days, consisting of only a small workshop and a sole proprietor working alone: upon receiving an order, he would be fully occupied with fulfilling that first order and unable to accept a second one. The cycle of receiving and completing orders-or fetching and executing instructions-is thus a serial process. Later, the boss discovered that taking orders did not require much time. With the help of an assistant, the two could work independently; this allowed the boss to accept a new order while simultaneously finishing the products for the previous one. In terms of CPU architecture, this corresponds to the separation of the instruction-fetching unit from the instruction-execution unit. Consequently, the CPU can fetch the next instruction in parallel while executing the current one. This represented a qualitative leap in CPU technology, shifting operations from serial to parallel processing and establishing the prototype of the instruction pipeline.
Once the CPU has completed the aforementioned step, the remaining challenge lies in enhancing parallel processing capabilities. Drawing inspiration from factory assembly lines, CPU designers broke down the execution of a single instruction into multiple distinct stages-or "micro-instructions"-thereby significantly reducing instruction complexity, simplifying logic design, and boosting speed. In CPUs utilizing pipelining technology, as soon as one instruction finishes its first "stage," the next instruction immediately enters the pipeline to begin execution. Clearly, this pipelining approach requires multiple execution units-a feature implemented in x86 chips.
